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Dr. Sandeep Mishra
Dr. Sandeep Mishra
Designation Assistant Professor,ECE
Educational Qualification Ph.D., M.Tech, B.Tech
Biography

Sandeep Mishra received the B.Tech and M.Tech degrees in Electronics and Communication Engineering from the Biju Patnaik University of Technology, Rourkela, India, in 2011 and 2013, respectively, and the Ph.D. degree in VLSI design from the National Institute of Technology Meghalaya at Shillong, in 2018. His research area of interest covers low-power VLSI design, memory design, and mixed signal circuits.

Journal Publications
  • S. Mishra, T. V. Mahendra, S. W. Hussain, and A. Dandapat, “The analogy of matchline sensing techniques for content addressable memory (CAM),” IET Computers & Digital Techniques, vol. 14, no. 3, pp. 87-96, Apr. 2020. (I.F. - 0.857)

  • S. Mishra, T. V. Mahendra, J. Saikia, and A. Dandapat, “A low-overhead dynamic TCAM with pipelined read-restore refresh scheme,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 5, pp. 1591-1601, May 2018. (I.F. - 3.934)

  • S. Mishra and A. Dandapat, “Energy-efficient adaptive match-line controller for large-scale associative storage,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 6, pp. 710-714, Jun. 2017. (I.F. - 3.25)

  • S. Mishra, T. V. Mahendra, and A. Dandapat, “A 9-T 833-MHz 1.72-fJ/bit/search quasi static ternary fully associative cache tag with selective matchline evaluation for wire speed applications,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 11, pp. 1910-1920, Nov. 2016. (I.F. - 3.934)

  • S. Mishra and A. Dandapat, “EMDBAM: A low power dual bit associative memory with match error and mask control,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 6, pp. 2142-2151, Jun. 2016. (I.F. - 1.946)

  • T. V. Mahendra, S. W. Hussain, S. Mishra, and A. Dandapat, “Energy-efficient precharge-free ternary content addressable memory (TCAM) for high search rate applications,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 7, pp. 2345-2357, Jul. 2020. (I.F. - 3.934)

  • T. V. Mahendra, S. W. Hussain, S. Mishra, and A. Dandapat, “Low discharge precharge free matchline structure for energy-efficient search using CAM,” Integration, the VLSI Journal, vol. 69, pp. 31-39, Nov. 2019. (I.F. - 1.15)

  • S. W. Hussain, T. V. Mahendra, S. Mishra, and A. Dandapat, “Match-line division and control to reduce power dissipation in content addressable memory”, IEEE Transactions on Consumer Electronics, vol. 64, no. 3, pp. 301-309, Aug. 2018. (I.F. - 2.083)

  • T. V. Mahendra, S. Mishra, and A. Dandapat, “Self controlled high performance pre-charge free content addressable memory,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 8, pp. 2388-2392, Aug. 2017. (I.F. - 1.946)

  • T. V. Mahendra, S. W. Hussain, S. Mishra, and A. Dandapat, “Precharge free dynamic content addressable memory,” Electronics Letters, vol. 54, no. 9, pp. 556-558, May 2018. (I.F. - 1.343)

  • F. Begum, S. Mishra, N. Islam, and A. Dandapat, “A 10-bit 2.33 fJ/conv. SAR-ADC with high speed capacitive DAC switching using a novel effective asynchronous control circuitry”, Analog Integrated Circuits and Signal Processing, vol. 100, no. 2, pp. 311-325, Aug. 2019. (I.F. - 0.823)

  • F. Begum, S. Mishra, and A. Dandapat, “Low power 10-bit flash ADC with divide and collate subranging conversion scheme”, Scientia Iranica, Transactions D: Computer Science & Engineering and Electrical Engineering, Accepted, pp. 1-20, 2019. (I.F. - 0.475)

Book Chapters
  • F. Begum, S. Mishra, N. Islam, and A. Dandapat, “Analysis and proposal of a flash subranging ADC architecture”, in Lecture Notes in Electrical Engineering, Springer, vol. 556, 2019, pp. 283-290.

  • F. Begum, S. Sarma, S. Mishra, and A. Dandapat, “Analysis of analog comparators using a 6-bit flash ADC architecture”, in Lecture Notes on Data Engineering and Communications Technologies, Springer, vol. 26, 2019, pp. 23-30.

International Conferences
  • S. W. Hussain, T. V. Mahendra, S. Mishra, and A. Dandapat, “Pseudo-static master-slave match-line scheme for sustainable-performance and energy-efficient content addressable memory,” in IEEE Region 10 Symposium (TENSYMP), Dhaka, 2020, pp. 1-4.

  • T. V. Mahendra, S. W. Hussain, S. Mishra, and A. Dandapat, “Design and implementation of drivers and selectors for content addressable memory (CAM),” in International Conference on Electronics and Communication Engineering, Xi'an, 2020, pp. 216-220.

  • T. V. Mahendra, S. W. Hussain, S. Mishra, and A. Dandapat, “Low match-line voltage swing technique for content addressable memory,” in International Conference on Smart Computing & Communications, Miri, 2019, pp. 325-329.

  • V. M. Tripathi, S. Mishra, J. Saikia, and A. Dandapat, ‘‘A low-voltage 13T latch-type sense amplifier with regenerative feedback for ultra speed memory access,’’ in 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), 2017, Hyderabad, pp. 341-346.

  • J. Saikia, S. Mishra, and A. Dandapat, ‘‘Large scale dynamic content addressable memory with hybrid matchline structure,’’ in Students' Technology Symposium (TechSym), 2016 IEEE, Kharagpur, Sep. 2016.

Achievements
  • Best paper award at TechSym-2016 conference for late breaking research presentation
  • 2001-2004: NRTS matching scholarship
  • 2002: Orissa state talent scholarship examination
Developed Software Tools for Research